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MDT10P23(CC )
1. General Description This EPROM-Based 8-bit micro-controller uses a fully static CMOS design technology to achieve high speed, small size, low power and high noise immunity. On chip memory includes 2K words EPROM and80 bytes static RAM. Four comparator inputs with external Vref (not for 18 pin package) are also provided. 2. Features u u u u Fully CMOS static design 8-bit data bus On chip EPROM size : 2 K words Internal RAM size : 80 bytes (72 general purpose registers, 8 special registers) u 36 single word instructions u 14-bit instructions u 2-level stacks u Operating voltage : 2.3V ~ 6.0 V u Operating frequency : 0 ~ 20 MHz u The most fast execution time is 200 ns under 20 MHz in all single cycle instructions except the branch instruction u Addressing modes include direct, indirect and relative addressing modes u Built-in Power-on Reset u 4 Channel comparator u Power edge-detector Reset u Sleep Mode for power saving u 8-bit real time clock/counter(RTCC) with 8-bit programmable prescaler u 4 types of oscillator can be selected by programming option:
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RCLow cost RC oscillator LFXTLow frequency crystal oscillator XTALStandard crystal oscillator HFXTHigh frequency crystal oscillator u 4 oscillator start-up time can be selected by programming option: 150 s, 20 ms, 40 ms, 80 ms u On-chip RC oscillator based Watchdog Timer(WDT) can be operated freely u 12 I/O(for 18 pins package),14 I/O(for 20 pins package),16 I/O(for 22/24 pins package) pins with their own independent direction control 3. Applications The application areas of this MDT10P23 range from appliance motor control and high speed automotive to low power remote transmitters/receivers, pointing devices, and telecommunications processors, such as Remote controller, small instruments, chargers, toy, automobile and PC peripheral ... etc
This specification are subject to be changed without notice. Any latest information
P. 1
2005/6
Ver. 1.4
MDT10P23(CC )
4. Pin Assignment A1G20PINS, A2G22PINS, A3G24PINS, A5 :18 PINS PPDIP,SSOP, KSKINNY A1P,A1S A3S PA5 PA2/CIC2 PA3/CIC3 RTCC /MCLR Vss PB0 PB1 PB2 PB3 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 PA4/VREF PA1/CIC1 PA0/CIC0 OSC1 OSC2 Vdd PB7 PB6 PB5 PB4 NC PA7 PA5 PA2/CIC2 PA3/CIC3 RTCC /MCLR Vss PB0 PB1 PB2 PB3 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 NC PA6 PA4/VREF PA1/CIC1 PA0/CIC0 OSC1 OSC2 Vdd PB7 PB6 PB5 PB4
A2K PA7 PA5 PA2/CIC2 PA3/CIC3 RTCC /MCLR Vss PB0 PB1 PB2 PB3 1 2 3 4 5 6 7 8 9 10 11 22 21 20 19 18 17 16 15 14 13 12 PA6 PA4/VREF PA1/CIC1 PA0/CIC0 OSC1 OSC2 Vdd PB7 PB6 PB5 PB4 A5P,A5S PA2CIC2 1 PA3/CIC3 2 RTCC 3 /MCLR 4 Vss 5 PB0 6 PB1 7 PB2 8 PB3 9 18 17 16 15 14 13 12 11 10 PA1/CIC1 PA0/CIC0 OSC1 OSC2 Vdd PB7 PB6 PB5 PB4
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P. 2
2005/6
Ver. 1.4
MDT10P23(CC )
5. Block Diagram
Stack Two Levels
EPROM 1KX14 (MDT10P23)
RAM 72X8 Port B
Port PB0~PB7 8 bits
10 bits 10 bits Program Counters Instruction Register 14 bits
Special Register
OSC2 OSC1
D0~D 7 MCLR Instruction Decoder
Port PA0~PA7 (22,24 pins PA0~PA5 (20 pins) PA0~PA3 (18 pins) Port A 8 bits
Oscillator Circuit
Control Circuit C R0~C R5 M M Comparat or mode Register
Power on Reset Power Down Reset Working Register ALU
Data 8-bit
Status Register
8-bit Timer/Counter
Prescale
WDT/OST Timer
RTCC
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P. 3
2005/6
Ver. 1.4
MDT10P23(CC )
6. Pin Function Description Pin Name PA0~PA7 I/O I/O Function Description PA0~PA3 : TTL input level or comparator input PA4 : TTL input level or comparator VREF input PA5~PA7 : TTL input level Port B, TTL input level Real Time Clock/Counter, Schmitt Trigger input levels Master Clear, Schmitt Trigger input levels Oscillator Input Oscillator Output Power supply Ground Unused ,do not connect
PB0~PB7 RTCC /MCLR OSC1 OSC2 Vdd Vss NC
I/O I I I O
7. Memory Map (A) Register Map Address 00 01 02 03 04 05 06 07 08~0F 10~1F 30~3F 50~5F 70~7F Description Indirect Addressing Register RTCC PC STATUS MSR Port A Port B Control register for comparator Internal RAM, General Purpose Register Internal RAM, Memory bank 0 Internal RAM, Memory bank 1 Internal RAM, Memory bank 2 Internal RAM, memory bank 3
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P. 4
2005/6
Ver. 1.4
MDT10P23(CC )
(1) IAR ( Indirect Address Register) : R0 (2) RTCC (Real Time Counter/Counter Register) : R1 (3) PC (Program Counter) : R2 Write PC, CALL --- always 0 LJUMP, JUMP, LCALL --- from instruction word RTWI, RET --- from STACK
A9
A8
A7~A0
Write PC, JUMP, CALL --- from STATUS b5 LJUMP, LCALL --- from instruction word RTWI, RET --- from STACK Write PC --- from ALU LJUMP, JUMP, LCALL, CALL --- from instruction word RTWI, RET --- from STACK (4) STATUS (Status register) : R3 Bit 0 1 2 3 4 5 Symbol C HC Z PF TF page Carry bit Half Carry bit Zero bit Power loss Flag bit Time overflow Flag bit ROM Page select bit : 00 : 000H --- 1FFH 01 : 200H --- 3FFH 7 XX General purpose bit Function
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P. 5
2005/6
Ver. 1.4
MDT10P23(CC )
(5) MSR (Memory Select Register) : R4 Memory Select Register : 00 : 10~1F 01 : 30~3F 10 : 50~5F 11 : 70~7F
b7
b6
b5
b4
b3
b2
b1
b0
Read only "1" Indirect Addressing Mode (6) PORT A : R5 PA7~PA0, I/O Register for 22, 24 pins PA5~PA0, I/O Register for 20 pins PA3~PA0, I/O Register for 18 pins (7) PORT B : R6 PB7~PB0, I/O Register (8) CMR(Comparator Mode Register) : R7 Bit 0 1 2 3 5:4 Function 0: Define PA0 as TTL input 1: Define PA0 as comparator input 0: Define PA1 as TTL input 1: Define PA1 as comparator input 0: Define PA2 as TTL input 1: Define PA2 as comparator input 0: Define PA3 as TTL input 1: Define PA3 as comparator input Reference Voltage select 00: 1/4 VDD 01: 1/2 VDD 10: 3/4 VDD 11: VREF (External pin and PA4 must be set to input) 7:6 Register bits
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P. 6
2005/6
Ver. 1.4
MDT10P23(CC )
9) TMR (Time Mode Register) Bit Symbol Prescaler Value Function RTCC rate WDT rate 000 1:2 1:1 001 1:4 1:2 010 1:8 1:4 011 1 : 16 1:8 100 1 : 32 1 : 16 101 1 : 64 1 : 32 110 1 : 128 1 : 64 111 1 : 256 1 : 128 Prescaler assignment bit : 0 X RTCC 1 X Watchdog Timer RTCC signal Edge : 0 X Increment on low-to-high transition on RTCC pin 1 X Increment on high-to-low transition on RTCC pin RTCC signal set : 0 X Internal instruction cycle clock 1 X Transition on RTCC pin
2X0
PS2X0
3
PSC
4
TCE
5
TCS
(10) CPIO A, CPIO B (Control Port I/O Mode Register) The CPIO register is "write-only" x"0", I/O pin in output mode; x"1", I/O pin in input mode. (11) EPROM Option by writer programming : A. FIRST WORD Oscillator Type RC Oscillator Oscillator Start-up Time 150 s 20 ms 40 ms 80 ms
LFXT Oscillator XTAL Oscillator HFXT Oscillator
Watchdog Timer control Watchdog timer disable all the time Watchdog timer enable all the time
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P. 7
2005/6
Ver. 1.4
MDT10P23(CC )
Power Edge Detect PED Disable Security bit Security Disable Security Enable
PED Enable (B) Program Memory Address 000- 3FF 3FF Program memory
Description
The starting address of the power on, external reset or WDT
8. Reset Condition for all Registers Register CPIO A CPIO B TMR IAR RTCC PC STATUS MSR PORT A PORT B CMR Address 00h 01h 02h 03h 04h 05h 06h 07h Power-On Reset 1111 1111 1111 1111 --11 1111 xxxx xxxx 1111 1111 0001 1xxx 100x xxxx xxxx xxxx xxxx xxxx 0000 0000 /MCLR Reset 1111 1111 1111 1111 --11 1111 uuuu uuuu 1111 1111 000# #uuu 100u uuuu uuuuuuuu uuuu uuuu uuuu uuuu WDT Reset 1111 1111 1111 1111 --11 1111 uuuu uuuu 1111 1111 000# #uuu 1uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
Note : uxunchanged, xxunknown, - xunimplemented, read as "0" #xvalue depends on the condition of the following table Condition /MCLR reset (not during SLEEP) /MCLR reset during SLEEP WDT reset (not during SLEEP) WDT reset during SLEEP Status: bit 4 U 1 0 0 Status: bit 3 u 0 1 0
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P. 8
2005/6
Ver. 1.4
MDT10P23(CC )
9. Instruction Set Mnemonic Operands NOP CLRWT SLEEP TMODE RET CPIO STWR LDWI I R R
Instruction Code 010000 00000000 010000 00000001 010000 00000010 010000 00000011 010000 00000100 010000 00000rrr 010001 1rrrrrrr 011000 trrrrrrr 111010 iiiiiiii 010111 trrrrrrr 011001 trrrrrrr 011010 trrrrrrr 011011 trrrrrrr 011100 trrrrrrr 011101 trrrrrrr 011110 trrrrrrr 010010 trrrrrrr 110100 iiiiiiii 010011 trrrrrrr 110101 iiiiiiii 010100 trrrrrrr 110110 iiiiiiii 011111 trrrrrrr 010110 trrrrrrr Instruction Code
Function No operation Clear Watchdog timer Sleep mode Load W to TMODE register Return Control I/O port register Store W to register Load register Load immediate to W
Operating None 0/WT
Status
TF, PF
0/WT, stop OSC TF, PF W/TMODE Stack/PC W/CPIO W/R R/t I/W [R(0~3)R(4~7)] /t R + 1/t R + 1/t W + R/t R W/t (R+/W+1/t) R 1/t R 1/t R a W/t i a W/W R a W/t i a W/W R o W/t /R/t R(n) /R(n-1), C /R(7), R(0)/C Operating r None None None None Z None None Z None C, HC, Z C, HC, Z Z None Z Z Z Z Z Z Z C Status
LDR R, t
SWAPR R, t Swap halves register INCR R, t Increment register
INCRSZ R, t Increment register, skip if zero ADDWR R, t Add W and register SUBWR R, t Subtract W from register DECR R, t Decrement register DECRSZ R, Decrement register, skip if t zero ANDWR R, t AND W and register ANDWI IORWI i XORWI RRR i i AND W and immediate Inclu. OR W and immediate IORWR R, t Inclu. OR W and register XORWR R, t Exclu. OR W and register COMR R, t Complement register R, t Rotate right register Function
Exclu. OR W and immediate i o W/W
Mnemonic Operands
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P. 9
2005/6
Ver. 1.4
MDT10P23(CC )
010101 trrrrrrr RLR R, t Rotate left register Clear working register R Clear register R, b Bit clear R, b Bit set R(n)/r(n+1), C/R(0), R(7)/C 0/W 0/R 0/R(b) 1/R(b) Skip if R(b)=0 Skip if R(b)=1 n/PC, PC+1/ Stack n/PC n/PC, PC+1/ Stack Stack/PC,i/W n/PC C Z Z None None None None None None None None None
010000 1xxxxxxx CLRW 010001 0rrrrrrr 0000bb brrrrrrr 0010bb brrrrrrr 0001bb brrrrrrr 0011bb brrrrrrr CLRR BCR BSR
BTSC R, b Bit Test, skip if clear BTSS R, b Bit Test, skip if set n n n i n Long CALL subroutine Long JUMP to address Call subroutine Return, place immediate to W JUMP to address
100nnn nnnnnnnn LCALL 101nnn nnnnnnnn LJUMP 110000 nnnnnnnn CALL 110001 iiiiiiii RTWI
11001n nnnnnnnn JUMP Note : W WT TMODE CPIO TF PF PC OSC Inclu. Exclu. AND : : : : : : : : : : :
Working register Watchdog timer TMODE mode register Control I/O port register Timer overflow flag Power loss flag Program Counter Oscillator Inclusive ` a' Exclusive ` o' Logic AND ` a'
b t
: : 0 1 R: C: HC : Z: / : x : i : n:
Bit position Target : Working register : General register General register address Carry flag Half carry Zero flag Complement Don't care Immediate data ( 8 bits ) Immediate address
10. Electrical Characteristics (Operating temperature at 25J). Sym Description Condition Min 2.3 Vdd=5V Vdd=5V -0.6 -0.6 Typ Max 6.0 1.0 1.0 Uni t V V V
Vdd Operating voltage VIL Input Low Voltage PA, PB RTCC, /MCLR
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P. 10
2005/6
Ver. 1.4
MDT10P23(CC )
Sym Description Condition Min Typ Max Uni t V V A V V V V A A A A A A 1.3 25.2 22.4 20.4 18.8 18.0 600 15 V mS mS mS mS mS nS A Vdd-0.8 V v 8 8 8 8 S S S S
VIH Input high Voltage PA, PB RTCC, /MCLR IIL Input leakage current VOL Output Low Voltage PA, PB VOH Output High Voltage PA, PB Islp Islp Sleep current (WDT disable) Sleep current (WDT enable)
Vdd=5V Vdd=5V Vdd=5V Vdd=5V, IOL=20mA Vdd=5V, IOL=5mA Vdd=5V, IOH= -20mA Vdd=5V, IOH= -5mA Vddx 2.3 ~ 6.0 V Vddx Vddx Vddx Vddx Vddx 2.3 V 3.0 V 4.0 V 5.0 V 6.0 V
2.0 3.3
Vdd Vdd +/-1 0.5 0.1 3.8 4.5 0.1 1 3 6 11 17 1.0
Vpr Power Edge-detector Reset Voltage Twdt The basic WDT time-out cycle time Vddx Vddx Vddx Vddx Vddx 2.3 V 3.0 V 4.0 V 5.0 V 6.0 V
1.1
TFLT /MCLR filter
Vddx 5.0 V
Icc Comparator Supply current (one Vdd=5.0v comparator) Vref Input reference voltage Comparator Response time V-=Vdd/4, V+=V- 0.2v V-=Vdd/2, V+=V- 0.2v V-=Vdd3/4, V+=V- 0.2v V-=VDD-0.8,V+=V 0.2v Vdd=2.5v ~6.0v Vdd=5.0v , V- = Vref V+ = (PA0~PA3)
---
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P. 11
2005/6
Ver. 1.4
MDT10P23(CC )
11. Operating Current Temperaturex25 J, the typical value as followings : 11.1 OSC TypexRC (OSC1&OSC2 Internal Cap about 10P); WDTEnable; Comparator Disable ; PED=Disable Vddx 5.0 V Cext. (F) Rext. (Ohm) 4.7 K 10.0 K 0P 47.0 K 100.0 K 300.0 K 470.0 K 4.7 K 10.0 K 3P 47.0 K 100.0 K 300.0 K 470.0 K 4.7 K 10.0 K 20P 47.0 K 100.0 K 300.0 K 470.0 K 4.7 K 10.0 K 100P 47.0 K 100.0 K 300.0 K 470.0 K Frequency (Hz) 7.76M 3.82M 848K 404K 135.6K 86K 6.8M 3.34M 740K 356K 119K 75.2K 4.16M 2.04M 452K 214.8K 75.2K 45.6K 1.57M 764K 167.2K 76.8K 26.6K 16.8K Current (A) 980 A 560 A 240 A 185 A 155 A 150 A 880 A 510 A 230 A 185 A 155 A 150 A 610 A 380 A 200 A 175 A 155 A 151 A 335 A 245 A 175 A 165 A 160 A 155 A
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P. 12
2005/6
Ver. 1.4
MDT10P23(CC )
Cext. (F) Rext. (Ohm) 4.7 K 10.0 K 300P 47.0 K 100.0 K 300.0 K 470.0 K Frequency (Hz) 672K 321.6K 70.4K 33.2K 11.1K 7.04K Current (A) 235 A 195 A 165 A 160 A 158 A 156 A
11.2 OSC TypexLF (OSC1&OSC2 Internal Cap about 10P); WDTEnable ; Comparator DisableQ PED=Disable Voltage/Frequency 2.3 V 3.0 V 4.0 V 5.0 V 6.0 V 32 K (EXT=50p) 7.0A 15.0A 35.0A 70.0A 130A 455 K 25A 45A 85A 140A 215A 1M 40A 65A 115A 180A 260A Sleep O1.0 A 3 A 6 A 11 A 17 A
11.3 OSC TypexXT (OSC1&OSC2 Internal Cap about 10P); WDTEnable ; Comparator Disable Q PED=Enable Voltage/Frequency 2.1 V 3.0 V 4.0 V 5.0 V 6.0 V 1M 50A 100A 210A 375A 645A 4M 120A 230A 400A 590A 850A 10 M 290A 490A 650A 1.3mA 1.6mA Sleep O1.0 A 3 A 6 A 11 A 17 A
11.4 OSC TypexHF (OSC1&OSC2 Internal Cap about 10P); WDTEnable ; Comparator DisableQ PED=Enable Voltage/Frequency 2.1 V 3.0 V 4.0 V 5.0 V 6.0 V 4M 150A 280A 510A 800A 1.3mA 10 M 320A 550A 910A 1.4mA 1.9mA 20 M X 925A 1.5mA 2.3mA 3.2mA Sleep O1.0 A 3 A 6 A 11 A 17 A
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P. 13
2005/6
Ver. 1.4
MDT10P23(CC )
11.5 Power Edge-detector Reset Voltage (Not in Sleep Mode), @ V ddx 5.0 V VprO 1.8~2.2 V Vpr
R
Vdd (Power Supply)
12. Port A Equivalent Circuit PA0-PA3
D I/O Control Latch
Q
I/O Control
C K
Q B
D Data O/P Latch G QB
Port I/O Pin
Write
Input Resistor
Data Bus QB Rea d Data I/P Latch G D S
0 TTL input level
1
+ comparator level VREF
Compartor Control
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P. 14
2005/6
Ver. 1.4
MDT10P23(CC )
PA4
D I/O Control Latch
Q
I/O Control
C K
Q B
D Data O/P Latch G Q B Input Resistor Data Bus Rea d QB Data I/P Latch G D TTL Input Level
Port I/O Pin
Write
comparator enable
3 2 Vref 1 S0 S1 0 CMR_4 CMR_5
3/4 VDD 1/2 VDD 1/4 VDD
PA5-PA7
D I/O Control Latch
Q
I/O Control
C K
Q B
D Data O/P Latch G Q B
Port I/O Pin
Write
Data Bus Rea d
QB Data I/P Latch
D Input Resistor TTL Input Level
G
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P. 15
2005/6
Ver. 1.4
MDT10P23(CC )
Port B Equivalent Circuit
D I/O Control Latch
Q
I/O Control
C K
Q B
Port I/O Pin D Data O/P Latch G Q B
Write
Data Bus Rea d
QB Data I/P Latch G
D Input Resistor TTL Input Level
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P. 16
2005/6
Ver. 1.4
MDT10P23(CC )
13. MCLRB and RTCC Input Equivalent Circuit
R U 1 K MCLRB Schmitt Trigger
R U 1 K
RTCC Schmitt Trigger
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P. 17
2005/6
Ver. 1.4
MDT10P23(CC )
14. External Capacitor Selection For Crystal Oscillator @ V ddx 5.0 V Osc. Type Resonator Freq. 20 MHz HF 10 MHz 4 MHz 10 MHz XT 4 MHz 1 MHz 1 MHz LF 455 K 32 K Capacity Range 10 pF ~ 50 pF 20 pF ~ 50 pF 10 pF ~ 30 pF 10 pF ~ 50 pF 10 pF ~ 50 pF 20 pF ~50 pF 20 pF ~ 30 pF 20 pF ~30 pF 20 pF ~30 pF
M D T 10P23 O1 SC OS C2
C1
C 2
To increase the stability of oscillator and the ability of anti-noise, the above values of the external capacitor are for reference only, but the higher capacitance also increases the start-up time.
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 18
2005/6
Ver. 1.4

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